1. Field of the Invention
The present invention relates to a low voltage differential signaling (LVDS) transmitter and, more specifically, relates to a LVDS transmitter with pre-emphasis function.
2. Description of Related Art
Digital signal data is usually transmitted in binary data signal, which has two voltage levels, representing data 0 or 1. In terms of signal waveform, high level and low level changing signals are used to transmit 0/1 data strings.
However, the circuit may have RC effect caused by resistance and capacitance, and therefore the rising side and the falling side cannot show step change and further cause data determining error. FIG. 1 schematically illustrates the phenomenon of RC delay effect. With reference to FIG. 1, in the case of a simple RC circuit 100, when an ideal pulse signal is input, the ideal pulse signal is transmitted to another terminal and output. The low level of the input pulse signal represents data 0, while the high level represents data 1. Due to RC circuit effect, the rising side and the falling side of the output pulse signal both have delay, and data determining error may be resulted. To solve this problem, the prior arts propose a pre-emphasis signal processing mechanism.
FIG. 2 schematically illustrates a diagram of a pre-emphasis mechanism of prior arts. With reference to FIG. 2, the data signal 102 has two levels, the position from low level to high level is the rising side, and the position from high level to low level is the falling side. To avoid RC delay effect, for example a pre-emphasis signal 104 is generated at the corresponding place of the rising side and the falling side. And the pre-emphasis signal 104 is added to the data signal 102, so that the speed of the rising side and the falling side is increased, therefore data determining (reading) error is avoided. As shown in FIG. 2, to generate the pre-emphasis signal 110, the data signal 106 may be delayed to obtain a data delay signal 108. And then the pre-emphasis signal 110 is generated based on the relation between the delay signal and the data signal.
A conventional signaling transmitting mechanism is described next. FIG. 3 illustrates a circuit diagram of a conventional LVDS transmitter. With reference to FIG. 3, the LVDS transmitter has two same circuit paths 120, 122 connected in parallel. The circuit path 120 comprises P transistors and N transistors which are connected in series through an output terminal. The gates of the two transistors are commonly connected to an input negative power supply VINN. The circuit path 122 also comprises P transistors and N transistors which are connected in series through an output terminal OUTN. The gates of the two transistors are commonly connected to an input positive power supply VINP. The two output terminals OUTN, OUTP are connected to two ends of a load 128. The circuit path 120 and 122 are connected between two current sources 124, 126, and are respectively driven by bias voltages BP, BN, and operate between a low voltage source VDD and a ground voltage. The controlling operation is performed through an inverter-type switch between two output terminals OUTN, OUTP. Current of the current source is passed out via the OUTP terminal or the OUTN terminal. At last, the desired differential voltage value is generated through the resistor load 128. Wherein, the BP and the BN, which are used to control the current value, are biases of the current source.
The traditional LVDS transmitter in FIG. 3 doesn't have pre-emphasis function. However, for example U.S. Pat. Nos. 6,288,581, 6,281,715, 6,977,534 and so on are also incorporated into the pre-emphasis circuit. Even so, the traditional LVDS transmitter still has some part to be further improved. Those in the ordinary arts still keep on researching and developing different circuit designs to enhance operation efficiency.